The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Memory integrated circuits (ICs) comprise memory arrays. The memory arrays may include memory cells of nonvolatile memory such as flash memory, phase-change memory, etc. The memory cells of nonvolatile memory may be electrically programmable and erasable. In the memory arrays, the memory cells are typically arranged in rows and columns. The memory cells in the rows and columns are addressed by word lines (WLs) and bit lines (BLs), respectively. The memory arrays comprise WL and BL decoders that select appropriate WLs and BLs, respectively, depending on the addresses of the memory cells selected during read/write operations.